MOS electric fuse, its programming method, and semiconductor device using the same

ABSTRACT

A programming method of a MOS electric fuse includes steps of preparing, as a fuse element, a MOS transistor which comprises second conductivity type first and second impurity regions formed to face with each other on an upper surface of a first conductivity type well on a semiconductor substrate, a gate dielectric film formed on the upper surface of the well at least between the first and second impurity regions, and a gate electrode formed through the gate dielectric film on the upper surface of the well between the first and second impurity regions and applying a first voltage to the gate electrode, and a second voltage different from the first voltage to the first impurity region, and short-circuiting the gate dielectric film only between the gate electrode and the first impurity region.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromprior Japanese Patent Application No. 2004-238537, filed Aug. 18, 2004,the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an electric fuse, and more particularlyto a MOS electric fuse which is configured to short-circuit a gatedielectric film and which is suitably applied to a MOS semiconductordevice.

2. Description of the Related Art

There has conventionally been known a semiconductor memory enablingelectric data writing (PROM) which uses a fuse element as a storageelement. The semiconductor memory of such a type is classified into afuse ROM which fuses the fuse element to store information, and a fuseROM which stores information making an insulator to a conductor bydielectric breakdown (may be referred to as antifuse).

The fuse ROM that breaks down the insulator to store the information isdisclosed in, for example, Jpn. Pat. Appln. KOKAI Publication. No.7-176703. In this example, a fuse of a 3-layer structure that sandwichesa silicon layer by refractory metal layers is disposed on asemiconductor substrate, and the silicon layer is converted into asilicide compound of low resistance by supplying a large current to thefuse, and the refractory metal layers are short-circuited from eachother.

Additionally, there has been known an electric fuse which electricallyconnects a source/drain of a MOS transistor to its substrate, applies ahigh voltage between the source/drain and a gate electrode to break downa gate dielectric film, and uses a resistance change therebetween. Thebreakdown of the fuse element to set a conductive state is calledprogramming. For example, a gate of a PMOSFET is grounded, and a highprogram voltage is applied to the source, the drain and the substrate.In this case, a channel is formed in the PMOSFET. When the appliedvoltage becomes higher, a withstand limit of the gate dielectric film isexceeded to break down the insulator, thereby making the gate filmconductive. In this way, the electric fuse is programmed.

In a large-capacity memory, a defective bit replacing technology thatuses a redundancy circuit is indispensable. A fuse is used to storedefective addresses. As a fuse of this type, there has been known amethod which fuses a polysilicon wiring or a transistor.

The programming of the MOS transistor type fuse is classified into twocases, that is, a case in which dielectric breakdown of the gatedielectric film occurs on the source (drain) and a case in whichdielectric breakdown occurs on the channel. Not only electriccharacteristics are different between the aforementioned two cases, butalso resistance values between the terminals are different depending ona position of the broken down dielectric film. When such a varianceoccurs in fuse electric characteristics after the breakdown of thedielectric film, a voltage margin is reduced at the reading time of thefuse element to cause a reduction in yield or reliability.

Thus, there has been a demand to realize a MOS transistor type fusewhich can make electric characteristics of an electric fuse uniform bykeeping a breakdown mode thereof constant.

BRIEF SUMMARY OF THE INVENTION

According to a first aspect of the invention, there is provided aprogramming method of a MOS electric fuse which comprises:

preparing, as a fuse element, a MOS transistor which comprises a firstimpurity region and a second impurity region, both of a secondconductivity type, formed to face with each other on an upper surface ofa well of a first conductivity type on a semiconductor substrate, a gatedielectric film formed on the upper surface of the well at least betweenthe first impurity region and the second impurity region, and a gateelectrode formed through the gate dielectric film on the upper surfaceof the well held between the first impurity region and the secondimpurity region; and

applying a first voltage to the gate electrode, and a second voltagedifferent from the first voltage to the first impurity region, andshort-circuiting the gate dielectric film only between the gateelectrode and the first impurity region.

According to a second aspect of the invention, there is provided anelectric fuse which comprises:

a semiconductor substrate;

a well of a first conductivity type formed on an upper surface of thesemiconductor substrate;

a first impurity region and a second impurity region of a secondconductivity type formed to face with each other on an upper surface ofthe well;

a gate dielectric film formed on the upper surface of the well at leastbetween the first impurity region and the second impurity region; and

a gate electrode formed through the gate dielectric film on the uppersurface of the well between the first impurity region and the secondimpurity region,

wherein substantially binary states of conduction and nonconduction areindependently set between the first impurity region and the gateelectrode and between the second impurity region and the gate electrode.

According to a third aspect of the invention, there is provided asemiconductor substrate which comprises:

a semiconductor substrate;

a plurality of wells of a first conductivity type formed on an uppersurface of the semiconductor substrate; and

a plurality of semiconductor structures formed in the plurality ofwells, each of the plurality of semiconductor structures comprising

-   -   -   a first impurity region and a second impurity region, both            of a second conductivity type, formed to face with each            other on an upper surface of each of the wells,        -   a gate dielectric film formed on the upper surface of the            well at least between the first impurity region and the            second impurity region and having portions covering the            first impurity region and the second impurity region, and        -   a gate electrode formed through the gate dielectric film on            the upper surface of the well held between the first            impurity region and the second impurity region and having            places opposed to the first impurity region and the second            impurity region,

    -   wherein, regarding a first opposed place of the first impurity        region and the gate electrode, and a second opposed place of the        second impurity region and the gate electrode, there are a first        state in which the first opposed place and the second opposed        place are both in insulated states, a second state in which the        first opposed place only is substantially short-circuited, a        third state in which the second opposed place only is        substantially short-circuited, and

    -   each of the plurality of semiconductor structures belongs to one        of the first state to the third state.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIGS. 1A and 1B are a connection diagram and a sectional view of aconventional MOS electric fuse;

FIG. 2 is a schematic sectional view illustrating a problem of theconventional MOS electric fuse;

FIG. 3 is a characteristic view illustrating a cause of a variance inelectric characteristics of the conventional MOS electric fuse;

FIGS. 4A and 4B are a connection diagram and a sectional view duringprogramming of an electric fuse (PMOS) according to a first embodiment;

FIGS. 5A and 5B are a connection diagram and a sectional view duringreading of the electric fuse according to the first embodiment;

FIGS. 6A and 6B are a connection diagram and a sectional view when theelectric fuse of the first embodiment comprises an NMOS;

FIGS. 7A and 7B are a connection diagram and a sectional view duringsource programming of an electric fuse according to a second embodiment;

FIGS. 8A and 8B are a connection diagram and a sectional view duringdrain programming of the electric fuse according to the secondembodiment;

FIGS. 9A and 9B are a connection diagram and a sectional view duringreading of the electric fuse according to the second embodiment;

FIG. 10 is a block diagram of an application circuit of the electricfuse according to the second embodiment;

FIG. 11 is a circuit diagram showing a specific example of theapplication circuit of FIG. 10;

FIGS. 12A to 12C are connection diagrams for programming and reading,and a sectional view during programming of an electric fuse according toa third embodiment; and

FIG. 13 is a block diagram showing an application circuit of aconventional MOS electric fuse.

DETAILED DESCRIPTION OF THE INVENTION

Before explanation of the embodiments of the present invention, problemsof a conventional MOS electric fuse will specifically be described. Forthe MOS electric fuse, two configurations similar to those shown inFIGS. 1A and 1B are conceivable. The fuse of FIG. 1A is referred to asan inversion type which connects a source/drain/substrate of a PMOS to aprogram voltage (VBP) terminal, and a gate electrode to a ground (VSS).The fuse of FIG. 1B is referred to as an accumulation type, in whichconnections to a VBP terminal and a VSS terminal are reverse to those ofFIG. 1A.

For example, as shown in FIG. 1A, the gate electrode of the PMOS isgrounded, and a high program voltage VBP is applied to the source, thedrain and the substrate. At this time, a channel is formed between thesource and the drain of the PMOS. When the program voltage VBP becomemuch higher, a withstand limit of a gate dielectric film is exceeded tobreak down a dielectric film, and a conductive state is set between thegate and the drain/source. In this way, the electric fuse is programmed.

In the aforementioned programming method, as shown in FIG. 2, breakdownplaces are classified into two cases: a case of breakdown on the source(or drain) (path A in FIG. 2), and a case of breakdown of the dielectricfilm on the channel (path B in FIG. 2). Electric characteristics aredifferent between the two cases because positions of conductive pointsare different. That is, in the former case, the gate electrode and thesource (or drain) are directly connected to each other through abreakdown portion in the case of the breakdown on the source or thedrain, and in the latter case, resistance values of a dielectric filmhorizontal direction are different depending on positions of the brokendown dielectric films in the case of the breakdown on the channel, andcurrent values supplied between the VPP and VSS terminals are differentas shown in FIG. 3. In such a conventional MOS electric fuse, a varianceoccurs in electric characteristics of the fuse after the dielectric filmbreakdown. Consequently, a voltage margin is deteriorated during readingof a fuse element to reduce yield or reliability.

According to the embodiments described below, a configuration of a MOSelectric fuse, a programming method, and the like are provided to solvethe aforementioned problems. That is, a gate dielectric film breakdownmode of the MOS electric fuse is limited to breakdown between a gate anda source (or drain), or breakdown substantially on a center between thesoured and the drain, and electric characteristics of the electric fuseare made uniform. Additionally, since programs can be independentlyexecuted in the case of the breakdown between the gate and the source,between the gate and the drain, a dielectric film between the gate andthe source or between the gate and the drain is selectively used toenable storage of information equivalent to the conventional twoelements by one fuse element. Thus, a quaternary (4-value) or ternary(3-value) memory can be formed by one element. Hereinafter, theembodiments will be described with reference to the accompanyingdrawings.

FIRST EMBODIMENT

FIG. 4A is a connection view of a PMOS electric fuse according to afirst embodiment, and FIG. 4B is a sectional view of the electric fuseschematically showing a voltage applied state during programming.

As shown in FIG. 4B, in an n-type well 2 formed in a semiconductorsubstrate 1, a source region (p-type impurity region) 3 and a drainregion (p-type impurity region) 4 are formed to face with each other. Agate electrode 6 is formed through a gate dielectric film 5 on an uppersurface of a portion of the well 2 sandwiched between the source region3 and the drain region 4. A material, dimensions and the like of the MOSstructure can be similar to those of a MOS structure of a MOS device onwhich a fused is mounted, for example, by a 90-nm process. No specialmaterials or dimensions need be employed for the electric fuse.

A program voltage VBP (positive potential) is connected to the gateelectrode 6, an optional voltage VBP′ (a positive potential, e.g., apower supply voltage VDD) are connected to the drain region 4, the well2, and the source region 3 is grounded (connected to VSS). However, thevoltage should form no channel between the source and the drain.According to the embodiment, VBP′=VBP is established.

In this state, when a VBP voltage is sufficiently high, a withstandlimit of the gate dielectric film 5 is exceeded to cause breakdown. Inthis case, a high voltage is only applied between the gate electrode 6and the source region 3, and the gate dielectric film 5 of this portionis broken down. In other words, the aforementioned connection enablesbreakdown of the gate dielectric film only between the gage electrode 6and the source region 3. Additionally, since the source region 3 and thedrain region 4 are completely symmetrical to each other, needless tosay, these portions are replaced by each other to make a connection andto enable programming.

In the foregoing, a similar program voltage VBP is applied to all of thegate electrode 6, the drain region 4, and the well 2. However, thevoltage VBP′ applied to the drain region 6, the well 2 is notnecessarily the program voltage VBP, but the voltage may be power supplyvoltage VDD. Additionally, the voltage applied to the drain region 6,and the well region 2 may be different. For example, a voltage appliedto the gate electrode 6 can be 2 to 5 V, and a voltage applied to thesource region 3 (or drain region 4) or the well can be 0 to 3 V. In thecase of programming in the described manner, the gate dielectric film isshort-circuited to lower resistance. However, a conductive/nonconductiveratio larger by 1000 times than a current ratio can be obtained.

Each of FIGS. 5A and 5B shows an example of a reading operation. Thesource region 3, the drain region 4, and the gate electrode 6 areprecharged once to VSS, and subsequently a normal power supply voltageVDD is applied to the gate electrode 6 after the source region 3 and thedrain region 4 are set in floating states. At this time, a voltage of aprogrammed region (e.g., source region 3) is quickly set to VDD, while anonprogrammed region (e.g., drain region 4) is maintained in the VSSstate. This voltage difference is amplified by a sense amplifier, andfuse data is written into a flip-flop or the like. Accordingly, it ispossible to read fuse information.

The embodiment has been described by taking the example of the PMOStype. However, the electric fuse can include an NMOS type by reversing apolarity. FIGS. 6A and 6B are a connection diagram and a sectional viewwhen an NMOS is used. Similar portions are denoted by similar numerals,and duplicated explanation will be omitted. VSS′ may be VSS (e.g.,ground potential), or different from VSS. Additionally, voltages of thewell 2 and the drain 4 may be different. VBP is a positive potential.

As described above, according to the first embodiment, since the gatedielectric film breakdown mode of the MOS electric fuse is limited tothe breakdown between the gate and the source (or drain), it is possibleto make electric characteristics of the electric fuse uniform.

In the aforementioned programming operation, the high voltage is appliedbetween the source and the gate to execute the programming. However,programming can subsequently be executed between the drain and the gate.During the programming operation between the gate and the drain, whetherthe gate dielectric film between the gate and the source has been brokendown or not has no influence at all on the breakdown operation betweenthe gate and the drain.

Accordingly, the gate dielectric film between the gate and the sourceand the gate dielectric film between the gate and the drain can beindependently broken down. Thus, it is possible to write quaternary(4-value) information in one fuse element. Such an example will bedescribed in a second embodiment.

SECOND EMBODIMENT

FIGS. 7A and 7B, and FIGS. 8A and 8B are schematic sectional views of anelectric fuse illustrating a programming method of the MOS electric fuseaccording to a second embodiment. FIGS. 7A and 7B show voltage appliedstates when a gate dielectric film on a source region is broken down(during source programming), which are similar to those of the firstembodiment of FIGS. 4A and 4B except for application of VBP′ to a drainregion. In this case, the VBP′ may be equal to VBP, or VDD.Additionally, VBP′ applied to a well 2 and VBP′ applied to a drainregion 4 may be different. However, the voltage should form no channelbetween the source and the drain. By such voltage application, a sourceside is programmed.

FIGS. 8A and 8B show voltage applied states when a drain side isprogrammed. The programming is similarly executed only by replacing thesource and the drain by each other in FIGS. 7A and 7B. As a result ofexecuting the programming of the drain side after the source side,dielectric film short-circuiting portions 7 are formed on both of thesource and drain regions 3 and 4.

FIGS. 9A and 9B are views showing an example of a reading operation whenthe drain side alone is programmed. The source region 3, the drainregion 4, and a gate electrode 6 are precharged to VSS. Subsequently, anormal power supply voltage VDD is applied to the gate electrode 6 afterthe source region 3 and the drain region 4 are set in floating states.At this time, a voltage of a programmed region (drain region 4) isquickly set to VDD, while a nonprogrammed region (source region 3)maintains a VSS state for a while. This voltage difference is amplifiedby a sense amplifier, and fuse data is written into a flip-flop or thelike. Accordingly, it is possible to read fuse information.

FIG. 10 is a block diagram of a semiconductor device on which anelectric fuse and a functional circuit are mounted. In an electric fuseelement 71, the source region 3 and the drain region 4 are outputterminals. The output terminals are connected to a data processingcircuit 74, which includes a sense amplifier, a flip-flop for storingelectric fuse data, or the like, through control circuits 72 and 73 asfunctional circuits. On the other hand, in the case of mounting theconventional electric fuse, a gate electrode of one electric fuseelement is connected to one control circuit 63, and this control circuit63 is connected to a data processing circuit 64 (see FIG. 13).

Thus, according to the electric fuse element of the embodiment, by usingthe source and the drain as the output terminals, an information amountof 2 channels, i.e., a maximum of 2 bits, can be held by one element. Inother words, the number of electric fuse elements necessary for holdingthe same information amount can be halved from that of the conventionalcase.

FIG. 11 is a circuit diagram showing an example of the control circuit,the data processing circuit of one channel of FIG. 10. Duringprogramming, a gate voltage of the electric fuse element 71 is set toVBP, VDD is applied to a gate of a driving transistor 81 in the controlcircuit 72, and a high-level Prog signal is applied to a gate of adriving transistor 82. During reading, first, a gate signal Prech of adriving transistor 83 in the data processing circuit 71 is set to a highlevel, and the drain region 4 of the electric fuse element 71 isprecharged to VSS. At this time, a gate of the electric fuse 71 is alsoset to VSS. Subsequently, a gate voltage of the electric fuse 71 is setto VDD, VDD is applied to the gate of the driving transistor 81 in thecontrol circuit 72, a Prog signal is set to a low level, and a voltageappearing in the drain region 4 of the electric fuse 71 is compared witha reference voltage Ref and amplified by a sense amplifier 84, and thenstored in a flip-flop 85. Thus, a one-time PROM can be configured.

As described above, according to the electric fuse of the secondembodiment, an information amount of a maximum of 4 values (1, 1), (1,0), (0, 1), and (0, 0) can be stored by one element, where “1” indicatesconduction, and “0” indicates nonconduction. Moreover, it is possible toconfigure a ternary (3-value) memory which uses three values of (0, 0),(1, 0), and (0, 1).

Furthermore, when the data processing circuit 74 is replaced by a sparedecoder or a memory cell matrix, it can be applied to a redundancycircuit of a memory. The second embodiment has been described by takingthe example of the PMOS. However, the electric fuse can include an NMOS.

THIRD EMBODIMENT

FIGS. 12A to 12C are connection and sectional views of an electric fuseaccording to a third embodiment. According to the third embodiment, theelectric fuse is of an inversion type, and employs a 2-terminalconfiguration in which a source region 3 and a drain region 4 areconnected to form one terminal, and a gate electrode 6 is an outputterminal.

During programming, for example, VSS is applied to each of the sourceregion 3, the drain region 4 and the gate electrode 6, and a programvoltage VBP is applied to a substrate (well) 2. As shown in FIGS. 12A to12C, if the electric fuse comprises a PMOSFET, and the VBP is a positivepotential, a depletion layer spreads from the source region 3 and thedrain region 4, and dielectric breakdown can be generated limitedly in agate dielectric film 5 on a substantial center between the source andthe drain.

During reading, the well 2, the source region 3, the drain region 4, andthe gate electrode 6 are precharged to, e.g., VSS. Subsequently, thewell 2, the source region 2, and the drain region 4 are set to, e.g.,VDD, and a potential change of the output terminal gate electrode 6 isdetected. The potential of the gate electrode 6 is changed to VDD if thegate dielectric film is short-circuited, and maintained at VSS if it isnot short-circuited.

Thus, according to the electric fuse of the third embodiment, since theshort-circuiting place of the gate dielectric film is limited to thesubstantial center between the source and the drain while theone-element and one-channel scheme is employed, it is possible torealize an electric fuse of a small characteristic variance. The thirdembodiment has been described by taking the example of the PMOS.However, the electric fuse can include an NMOS.

Additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the invention in its broader aspects isnot limited to the specific details and representative embodiments shownand described herein. Accordingly, various modifications may be madewithout departing from the spirit or scope of the general inventiveconcept as defined by the appended claims and their equivalents.

1. A programming method of a MOS electric fuse comprising: preparing, asa fuse element, a MOS transistor which comprises a first impurity regionand a second impurity region, both of a second conductivity type, formedto face with each other on an upper surface of a well of a firstconductivity type on a semiconductor substrate, a gate dielectric filmformed on the upper surface of the well at least between the firstimpurity region and the second impurity region, and a gate electrodeformed through the gate dielectric film on the upper surface of the wellheld between the first impurity region and the second impurity region;and applying a first voltage to the gate electrode, and a second voltagedifferent from the first voltage to the first impurity region, andshort-circuiting the gate dielectric film only between the gateelectrode and the first impurity region.
 2. The method according toclaim 1, wherein the first voltage and the second voltage form nochannels between the first impurity region and the second impurityregion.
 3. The method according to claim 1, wherein the firstconductivity type is an n type, and the MOS transistor is a PMOStransistor.
 4. The method according to claim 3, wherein the firstvoltage is a positive potential, and the second voltage is a groundpotential.
 5. The method according to claim 1, wherein the firstconductivity type is a p type, and the MOS transistor is an NMOStransistor.
 6. The method according to claim 5, wherein the firstvoltage is a ground potential, and the second voltage is a positivepotential.
 7. The method according to claim 1, further comprisingapplying a third voltage to the gate electrode, and a fourth voltagedifferent from the third voltage to the second impurity region, andshort-circuiting a portion only between the gate electrode and thesecond impurity region.
 8. A programming method of a MOS electric fusecomprising: preparing, as a fuse element, a MOS transistor whichcomprises a first impurity region and a second impurity region, both ofa second conductivity type, formed to face with each other on an uppersurface of a well of a first conductivity type on a semiconductorsubstrate, a gate dielectric film formed on the upper surface of thewell at least between the first impurity region and the second impurityregion, and a gate electrode formed through the gate dielectric film onthe upper surface of the well held between the first impurity region andthe second impurity region; and applying a first voltage to the gateelectrode, and a second voltage different from the first voltage to thewell, and substantially short-circuiting the gate dielectric filmbetween the gate electrode and a surface of the well on a substantialcenter alone between the first impurity region and the second impurityregion.
 9. The method according to claim 8, wherein the semiconductorwell is an n type, and the MOS transistor is a PMOS transistor.
 10. Themethod according to claim 9, wherein the first voltage is a groundpotential, and the second voltage is a positive potential.
 11. Themethod according to claim 8, wherein the semiconductor well is a p type,and the MOS transistor is an NMOS transistor.
 12. The method accordingto claim 11, wherein the first voltage is a positive potential, and thesecond voltage is a ground potential.
 13. A MOS electric fusecomprising: a semiconductor substrate; a well of a first conductivitytype formed on an upper surface of the semiconductor substrate; a firstimpurity region and a second impurity region of a second conductivitytype formed to face with each other on an upper surface of the well; agate dielectric film formed on the upper surface of the well at leastbetween the first impurity region and the second impurity region; and agate electrode formed through the gate dielectric film on the uppersurface of the well between the first impurity region and the secondimpurity region, wherein substantially binary states of conduction andnonconduction are independently set between the first impurity regionand the gate electrode and between the second impurity region and thegate electrode.
 14. The MOS electric fuse according to claim 13, whereinthe well is electrically connected to the gate electrode.
 15. A MOSelectric fuse device comprising: a semiconductor substrate; a well of afirst conductivity type formed on an upper surface of the semiconductorsubstrate; a first impurity region and a second impurity region, both ofa second conductivity type, formed to face with each other on an uppersurface of the well; a gate dielectric film formed on the upper surfaceof the well at least between the first impurity region and the secondimpurity region; and a gate electrode formed through the gate dielectricfilm on the upper surface of the well held between the first impurityregion and the second impurity region, wherein substantially binarystates of conduction and nonconduction are set only between asubstantial center between the first impurity region and the secondimpurity region and a portion of the gate electrode opposed to thecenter.
 16. The MOS electric fuse device according to claim 15, whereinthe well is electrically connected to the first impurity region and thesecond impurity region.
 17. A semiconductor device comprising: asemiconductor substrate; a plurality of wells of a first conductivitytype formed on an upper surface of the semiconductor substrate; and aplurality of semiconductor structures formed in the plurality of wells,each of the plurality of semiconductor structures comprising a firstimpurity region and a second impurity region, both of a secondconductivity type, formed to face with each other on an upper surface ofeach of the wells, a gate dielectric film formed on the upper surface ofthe well at least between the first impurity region and the secondimpurity region and having portions covering the first impurity regionand the second impurity region, and a gate electrode formed through thegate dielectric film on the upper surface of the well held between thefirst impurity region and the second impurity region and having placesopposed to the first impurity region and the second impurity region,wherein, regarding a first opposed place of the first impurity regionand the gate electrode, and a second opposed place of the secondimpurity region and the gate electrode, there are a first state in whichthe first opposed place and the second opposed place are both ininsulated states, a second state in which the first opposed place onlyis substantially short-circuited, a third state in which the secondopposed place only is substantially short-circuited, and each of theplurality of semiconductor structures belongs to one of the first stateto the third state.
 18. A semiconductor device comprising: asemiconductor substrate; a well of a first conductivity type formed onan upper surface of the semiconductor substrate; a first impurity regionand a second impurity region, both of a second conductivity type, formedto face with each other on an upper surface of the well; a gatedielectric film formed on the upper surface of the well at least betweenthe first impurity region and the second impurity region; a gateelectrode formed through the gate dielectric film on the upper surfaceof the well held between the first impurity region and the secondimpurity region; a first terminal connected to the first impurityregion; a second terminal connected to the second impurity region; athird terminal connected to the gate electrode; a fourth terminalconnected to the well; a first functional circuit connected to the firstterminal; and a second functional circuit connected to the secondterminal, wherein binary states of conduction and nonconduction aresubstantially set between the first terminal and the third terminal andbetween the second terminal and the third terminal.
 19. Thesemiconductor device according to claim 18, wherein the first functionalcircuit and the second functional circuit include sense amplifiers toread the binary states.
 20. The semiconductor device according to claim18, wherein the first functional circuit and the second functionalcircuit include memory cells for a memory circuit.